1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to an apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device.
2. Description of Related Art
When manufacturing integrated circuit chips, it is important to be able to test the operation of the modules, e.g., processors, on the integrated circuit chips in order to ensure their proper operation. The time required to test such modules significantly adds to the total cost of manufacturing the integrated circuit chip. Thus, if it is possible to improve upon the test time, the cost of manufacturing integrated circuit chips may be reduced. Moreover, efficient debug and failure analysis of such modules helps in reducing the total time to market as well as increases the yield, resulting in overall reduction in cost of manufacturing the integrated circuit chip.
The usual manner of testing a module on an integrated circuit chip is the application of signal patterns using an external tester and scan chains provided on the integrated circuit chip. Alternatively, an internal built-in-self-test (BIST) engine and scan chains may be used. While these test methods are necessary for exhaustive testing of the integrated circuit device, they are time consuming processes that require external test equipment to extract test results from the integrated circuit chip and perform the necessary analysis for determining if the integrated circuit chip is operating properly.
One approach to detecting faults in modules of an integrated circuit chip involves comparing a module on an integrated circuit chip with a copy of the module. Such an approach is referred to as fault detection by duplication and is considered to be conceptually the most simple fault detection technique for integrated circuit chip modules. An example of fault detection by duplication is described in Prasad, “Fault Tolerant Digital Systems,” IEEE Potentials, vol. 8, no. 1, pp. 17-21, February 1989, which is hereby incorporated by reference.
There are significant drawbacks to known fault detection by duplication mechanisms. For example, in addition to the overhead of having to provide a duplicate module, fault detection by duplication requires an external comparator (external to the integrated circuit chip) for comparing the outputs of the module under test and the duplicate module. In addition, such fault detection is not able to monitor important internal signals for comparison, making fault detection much more time consuming. Thus, it would be beneficial to eliminate the need for external test equipment that provides an external comparator and provide a mechanism that permits monitoring of important internal signals.